In the art of microelectronics deep trenches are frequently used. By way of example, in the field of vertical power MOS devices, deep trenches are used for electrically isolating adjacent semiconductor regions of the device. A trench is typically formed using a photolithographic mask and a highly anisotropic dry etching process of the semiconductor substrate. This process is suitable for forming trenches up to 10 .mu.m deep and with a width of 1 .mu.m or less, with rather vertical walls.
If trenches are used for the purpose of isolating different semiconductor regions in the horizontal direction with respect to the surface of the semiconductor, the conventional process allows for forming structures with limited overhead in terms of semiconductor area compared to other isolation techniques. An alternative isolation technique known as junction isolation provides for forming PN junctions. These junction regions which, to reach the required depth, are subject to a significant lateral diffusion. This is so even if the problem of area occupation in junction isolation can be partially reduced by using high implantation energies, exploiting channeling effects, and activating the implanted species by means of rapid thermal processes. It is still necessary to invert the conductivity type of the starting semiconductor region after the implanted dopant has been activated.
By the use of trenches all these problems can be avoided, and a reduction of the semiconductor area occupied can be achieved. It is however known that, e.g. when the trenches are used for electrical isolation, a dopant must be implanted into the bottom of the trench. The dopant is of the same conductivity type as that of semiconductor region of interest.
By way of example, in FIG. 1 there is depicted a cross-section of a NPN vertical transistor that is to be isolated from the remaining devices integrated in the same chip. The chip comprises a P type substrate 1, over which an N+ buried layer 2 has been formed and, over layer 2, an N type epitaxial layer 3. A P type base region 4 is formed in the N type epitaxial layer 3, and a base terminal B contacts the P base region 4. An N type emitter region 5 is formed inside the P type base region 4, and an emitter terminal E contacts the emitter region 5. An N+ sink region 6 is formed in the N type epitaxial layer 3 and extends down to the buried layer 2. A collector terminal C is connected to the N+ sink region 6. A deep trench 7 is formed in the N type epitaxial layer 3, the N+ buried layer 2, and part of the substrate 1.
The deep trench 7 isolates the NPN vertical transistor from other devices which are to be integrated as shown at the left thereof in the drawing. Such other devices may include, for example, another NPN vertical transistor of which there is shown only the N+ sink region 6' and the respective collector terminal C'. The trench 7 is conventionally filled with dielectric material, typically an oxide 8.
An inverted region can built-up in the semiconductor at the interface between the semiconductor and the dielectric material filling the trench. This is especially so if as shown in the drawing, the bottom end of the trench is within lightly doped P type semiconductor regions (that is the most common situation). The inverted region is equivalent to the conductive channel of a parasitic MOS transistor, and short-circuits the collector (buried layer 2) of the NPN transistor to the portions of the N+ buried layer 2 outside the NPN transistor region beyond the trench. Furthermore, an NPN lateral transistor is associated with the structure, and formed by the portion of the buried layer 2 in the NPN vertical transistor region, the substrate 1, and the portion of the buried layer 2 outside the NPN vertical transistor region beyond the trench.
To overcome the above-referred drawbacks, there is conventionally performed an ion implantation inside the trench to form a P+ well 9 in the semiconductor substrate 1 at the bottom of the trench 7 (FIG. 2). The P+ well 9 prevents the previously described parasitic MOS transistor from turning on, since the dopant concentration at the semiconductor/dielectric interface is increased, and additionally lowers the gain of the parasitic lateral NPN transistor.
However, performing a selective implant inside the trench to form the P+ well region 9 at the bottom thereof is inherently difficult. In particular, it is necessary to confine all the implanted dopant ions at the bottom of the trench. Clearly, over the planar top surface of the chip a mask layer is to be provided, and the implant must be performed orthogonally to the top surface of the chip. However, even in this way a fraction of the implanted dopant ions hits the lateral walls of the trench, since the walls are not perfectly vertical and the implanted ion beam cannot be perfectly collimated. In fact, it is quite difficult to form trenches with vertical walls uniformly in the entire chip area, and the degree of collimation of the implanted ion beams can vary inside the area to be implanted. The ions reaching the substrate have a predetermined angular distribution in terms of flux per unit of solid angle, which is quite high in the primary direction of the beam and that decreases more or less rapidly for directions which become more and more different from the main one.
For the above reasons, a fraction of the implanted dopant ions is actually implanted into the lateral walls of the trench. Such a fraction is higher the higher the inclination of the lateral walls of the trench and the worse the collimation of the implantation beam. By way of example, if the lateral walls of the trench are inclined at 10.degree. and assuming that the implantation beam is perfectly collimated, then a dose of dopant approximately equal to 17% of the total implanted dose is implanted into the lateral walls of the trench.
In practice, the inclination of the lateral walls of the trench is not constant, and increases downward toward the bottom of the trench, where the lateral walls are nearly vertical. Since the implant is performed orthogonally to the top surface of the chip and this direction normally coincides with a crystallographic axis of the semiconductor substrate, to avoid problems of "channeling" it is necessary to grow a layer of oxide over the surface. This, however, does not overcome the problem of implantation of dopants into the lateral walls.